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| Verilog HDL - A Guide to Digital Design and Synthesis, Literatura, Verilog |
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[ Pobierz całość w formacie PDF ] Verilog HDL A guide to Digital Design and Synthesis Samir Palnitkar SunSoft Press 1996 PART 1 BASIC VERILOG TOPICS 1 1 Overview of Digital Design with Verilog HDL 3 2 Hierarchical Modeling Concepts 11 3 Basic Concepts 27 4 Modules and Ports 47 5 Gate-Level Modeling 61 6 Dataflow Modeling 85 7 Behavioral Modeling 115 8 Tasks and Functions 157 9 Useful Modeling Techniques 169 PART 2 Advance Verilog Topics 191 10 Timing and Delays 193 11 Switch- Level Modeling 213 12 User-Defined Primitives 229 13 Programming Language Interface 249 14 Logic Synthesis with Verilog HDL 275 PART3 APPENDICES 319 A Strength Modeling and Advanced Net Definitions 321 B List of PLI Rountines 327 C List of Keywords, System Tasks, and Compiler Directives 343 D Formal Syntax Definition 345 E Verilog Tidbits 363 F Verilog Examples 367 Part 1 BasicVerilog Topics Overview of Digital Design with Verilog HDL Evolution of CAD, emergenceof HDLs, typical HDL-based design flow, why Verilog HDL?, trends in HDLs. Hierarchical Modeling Concepts Top-down and bottom-up design methodology,differences between modules and module instances,parts of a simulation,design block, stimulus block. Basic Concepts Lexical conventions, data types, system tasks, compiler directives. Modules and Ports Module definition, port declaration, connecting ports, hierarchicalname referencing. Gate-Level Modeling Modeling using basic Verilog gate primitives, descriptionof andlor and buflnot type gates, rise, fall and turn-off delays, min, max, and typical delays. Dataflow Modeling Continuous assignments, delay specification,expressions,operators, operands, operator types. Behavioral Modeling Structuredprocedures, initial and always, blocking'and nonblocking statements,delay control,event control,conditional statements,multiway branching, loops, sequentialand parallel blocks. Tasks and Functions Differencesbetween tasks and functions, declaration, invocation. Useful Modeling Techniques Proceduralcontinuousassignments, overridingparameters,conditional compilation and execution, useful system tasks. Verilog HDL: A Guide to Digital Design and Synthesis [ Pobierz całość w formacie PDF ] |