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| Verilog.VHDL.Golden.Reference.Guide, Literatura, Verilog |
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[ Pobierz całość w formacie PDF ] The Verilog ® Golden Reference Guide DOULOS Version 1.0, August 1996 © Copyright 1996, Doulos, All Rights Reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, without the prior written permission of DOULOS. Printed in the United Kingdom of Great Britain and Northern Ireland. Verilog-XL TM is a trademark and Verilog ® a registered trademark of Cadence Design Systems Inc. DOULOS Church Hatch, 22 Market Place, Ringwood. Hampshire. BH24 1AW England. Tel (+44) (0)1425 471223 Fax (+44) (0)1425 471573 Email info@doulos.co.uk Preface The Verilog Golden Reference Guide is a compact quick reference guide to the Verilog hardware description language, its syntax, semantics, synthesis and application to hardware design. The Verilog Golden Reference Guide is not intended as a replacement for the IEEE Standard Verilog Language Reference Manual. Unlike that document, the Golden Reference guide does not offer a complete, formal description of Verilog. Rather, it offers answers to the questions most often asked during the practical application of Verilog, in a convenient reference format. Nor is The Verilog Golden Reference Guide intended to be an introductory tutorial. Information is presented here in a terse reference format, not in the progressive and sympathetic manner necessary to learn a subject as complex as Verilog. However, acknowledging that those already familiar with computer languages may wish to use this guide as a Verilog text book, a brief informal introduction to the subject is given at the start. The main feature of The Verilog Golden Reference Guide is that it embodies much practical wisdom gathered over many Verilog projects. It does not only provide a handy syntax reference; there are many similar books which perform that task adequately. It also warns you of the most common language errors, gives clues where to look when your code will not compile, alerts you to synthesis issues, and gives advice on improving your coding style. The Verilog Golden Reference Guide was developed to add value to the Doulos range of Verilog training courses, and also to complement HDL PaceMaker, the Verilog Computer Based Training package from Doulos. 3 Using This Guide The main body of this guide is divided into three main parts, each of which is organised alphabetically. Each section is indexed by a key term which appears prominently at the top of each page. Often you can find the information you want by flicking through the guide looking for the appropriate key term. If that fails, there is a full index at the back. Most of the information in this guide is organised around the Verilog syntax headings, but there are additional special sections on Coding Standards, Design Flow, Errors, Reserved Words and, after the main alphabetical reference section, Compiler Directives, System Tasks and Functions and Command Line Options. If you are new to Verilog, you should start by reading A Brief Introduction to Verilog, which follows overleaf. The Index Bold index entries have corresponding pages in the main body of the guide. The remaining index entries are followed by a list of appropriate page references in the alphabetical reference sections, given in order of importance. Key To Notation Used To Define Verilog Syntax The syntax definitions are written to look like examples wherever possible, but it has been necessary to introduce some extra notation. In brief, square brackets [] enclose optional items, three dots ... means repetition, and curly brackets {} enclose comments. ItalicNames represent parts of the syntax defined elsewhere. A full description of the notation follows: Curly brackets {} enclose comments that are not part of the Verilog syntax being defined, but give you further information about the syntax definition. Bold curly brackets {} are part of the Verilog syntax (concatenation operator). Syntax enclosed in square brackets [] is optional. Bold square brackets [] are part of the Verilog syntax (vector range, bit and part select, memory element). ... means zero or more repetitions of the preceding item or line, or means a list, as follows: Item ... means zero or more repetitions of the Item. , ... means repeat in a comma separated list (e.g. A, B, C). 4 There must be at least one item in the list. There is no , at the end of the list. Words in lower-case letters are reserved words, built into the Verilog language (e.g. module) Capitalised Words (not in italics) are Verilog identifiers, i.e. user defined names that are not reserved identifiers (e.g. InstanceName). Italic Words are syntactic categories, i.e. the name of a syntax definition given in full elsewhere. A syntactic category can be either defined on the same page, defined on a separate page, or one of the special categories defined below. Italics = indicates a syntactic category which is defined and used on the same page. Special syntactic categories: MinTypMaxExpression is defined with Expression . UnsignedNumber is defined with Number . SomethingExpression = Expression , where the Something gives information about the meaning of the expression (e.g. ConstantExpression, ConstantMinTypMaxExpression ). 5 [ Pobierz całość w formacie PDF ] |